Warped FIR implementation on a SHARC
It takes 5 lines (CPU cycles), whilst the normal FIR is just one line – thus a SHARC can run a set of 4 FIRs of more than 200 taps each, but only 42 taps with WFIR.
lThe WFIR structure was coded in assembly on the AD21061 and on the AD21065L processors: here the assembly code of the main cycle is shown:
LCNTR=Wfilter_taps-1 , DO wmac_rr UNTIL LCE;
F12=F2*F4, F9=dm(I5,M7), F4=pm(I9,M8);
F10=F2*F5, F8=F8+F12, F9=dm(I5,M6);
F1=F9-F10, F9=dm(I5,0);
F10=F1*F7, dm(I5,M7)=F2;
wmac_rr:F2=F9+F10;